Keeping up Moore’s law in the interconnect era: from novel materials to interface optimization.
In today’s microelectronic chips, interconnects have replaced transistors as the main determinants of performance. This development will only escalate in the future when characteristic wire dimensions approach 10 nm, and thus the future of CMOS nanoelectronic scaling will have to center around interconnects. In contrast to transistors, solutions can only come through materials innovation by introducing new materials and optimizing interfaces to simultaneously reduce the resistance of interconnects and improve their reliability. In this presentation, the challenges for interconnect scaling will be introduced and the current status of the research on novel interconnect metallization schemes will be reviewed with a focus on the effect of the ubiquitous interfaces on the interconnect performance.
Principal member of technical staff Thin Films Group at Imec Leuven
Christoph Adelmann obtained a Ph.D. degree in condensed matter physics from Université Grenoble Alpes in 2002 researching III-V nitride semiconductors at the CEA Grenoble. Until 2006, he was a post-doctoral research associate with the Department of Chemical Engineering and Materials Science at the University of Minnesota, focusing on spintronic materials and devices. He joined the Thin Films Group at imec in Leuven, where he is currently a principal member of technical staff, focusing on metallic and dielectric materials for logic, interconnects, and memory and on novel devices for nanoelectronic applications. He has co-authored over 240 scientific publications in peer-reviewed journals or conference proceedings as well as 7 granted patents and 25 pending patent applications.
