Interconnects have replaced transistors as the main determinants of performance in modern microelectronic chips. When wire dimensions approach 10 nm, new materials for interconnects are needed to keep up Moore’s law, Christoph Adelmann from Imec says. He’ll talk about the latest research on novel interconnects at the MicroNano Conference 2018.
Current CMOS-designs have billions of transistors as scaling down chip design is progressing. But the smaller chips get, the more problems arise. And not only for the transistor design, Adelmann, working at the Thin Films Group at Imec Leuven, explains: “When people historically talk about scaling and Moore’s law, they think of transistors and how to make them smaller and historically also faster. However, when one looks at how area scaling is done, transistors are only one dimension. The other dimension is the interconnect scaling. The interconnect is the wiring between transistors, logic circuits, and ultimately functional blocks, like logic cores, memory, in the chip.”
He continues: “This can be understood quite literally since the characteristic distance in one direction of a circuit is given by the distance between transistors, the gate pitch, whereas the characteristic dimension is given by the smallest distance between interconnect wires. So to scale the area of a circuit (e.g. an SRAM cell), both the distance between transistors as well as between interconnect wires needs to be reduced. In future technology nodes, the scaling of the transistor gate pitch will become increasingly difficult and thus the metal pitch scaling becomes even more important.”
And when further downscaling is sought-after, more challenges come up, Adelmann says: “The interconnect performance has become a real limiting factor for overall circuit performance. This concerns both the resistance of the wires that is ever increasing when they become smaller as well as their reliability. Especially effects like electro migration have really become a problem. So it’s now fair to say that interconnect performance is really a main factor that determines chip performance and reliability. This is why interconnect R&D has become at least as important as transistor R&D. This is very likely to continue and even accentuate in the future.”
Some companies are looking for alternatives. Adelmann: “Currently, Intel has announced to use cobalt as an alternative metal in the 10 nm technology node. Ruthenium is also an interesting option that is still further out than cobalt. At imec, we are indeed currently working strongly on ruthenium. Main parameters for materials are resistivity in small dimensions as well as electro migration resistance. In my presentation I will cover these alternatives rather extensively.” Link to: https://ieeexplore.ieee.org/document/8456484
Adelmann also explains where the main focus is in current research: “A key research task is to reduce the thickness of the barrier and liner layers since they occupy volume in the interconnect wire and conduct much less than the main conductor Such layers are already only 1-3 nm thick and it is difficult to reduce their thickness further. When the wire width becomes really small, let’s say 10 nm and less, which should happen in a few years from now, they will still occupy most of the line and there is essentially no more space for the main conductor material left. Therefore, we really looking for materials that don’t need such a barrier or liner layer. However, adhesion still needs to be good, so we have to find a material that has also good adhesion to typical dielectrics, which adds to the selection criteria that are mentioned above. This is not a trivial task since many metals typically show very poor adhesion with dielectrics.”
When looking at optical computing, Adelmann is excited about the prospects of this technology. But it has it’s limitations, he says: “Currently, optical I/O is researched for connections between individual chips. It is possible that optical I/O will also become one day competitive on a scale that will enable optical interconnects between different parts on a chip, e.g. the logic cores and memory. However, optical interconnects cannot be miniaturized to the level needed to connect individual transistors since photonic waveguides are too large. Plasmonics may allow some further miniaturization but to which level is still an open research topic. Also, the overhead that is needed to convert between optical and electrical signals will use much space and energy and therefore this will happen only at a few places on a chip. However, the question at what dimensions and connection lengths the transition between electrical and optical interconnects will happen is indeed very interesting and will certainly evolve in the future.”
‘Keeping up Moore’s law in the interconnect era: from novel materials to interface optimization’, a presentation by Christoph Adelmann, will be held at 09:45 on Tuesday December 11th 2018 at the Beurs van Berlage, Amsterdam, The Netherlands. This will be the 13th edition of the MicroNanoConference.